CICC 2001 A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance
نویسندگان
چکیده
Abstract Accurate integrity assessment of on-chip clock lines is difficult without any a priori knowledge about their inductance at an early stage in the clock design process. This paper introduces an efficient approach to estimate the bounds of on-chip clock wire inductance at the very beginning of the design stages. With this information, more accurate waveforms along the clock distribution networks can be obtained thus greatly reducing the overall length of design cycles.
منابع مشابه
A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance
Abstract Accurate integrity assessment of on-chip clock lines is difficult without any a priori knowledge about their inductance at an early stage in the clock design process. This paper introduces an efficient approach to estimate the bounds of on-chip clock wire inductance at the very beginning of the design stages. With this information, more accurate waveforms along the clock distribution n...
متن کاملA Unified RLC Model for High-Speed On-Chip Interconnects
In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width ( ) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new anal...
متن کاملHigh Frequency Characterization and Modeling of VLSI On-Chip Interconnects
| Modeling of on-chip inductance for chips with realistic power/ground wires and grids is presented. Analytical formulae as well as eld solvers are used to analyze inductance of on-chip structures including power/ground grids, ground plane and substrate e ects. Insights and design guidelines to reduce wire inductance are demonstrated. An accurate capacitance modeling approach is also presented.
متن کاملA 150nW, 5ppm/o C, 100kHz On-Chip clock source for ultra low power SoCs
This paper presents an ultra low power clock source using a 1μW temperature compensated on-chip digitally controlled oscillator (OscCMP) and a 100nW uncompensated oscillator (OscUCMP) with respective temperature stabilities of 5ppm/C and 1.67%/C. A fast locking circuit re-locks OscUCMP to OscCMP often enough to achieve a high effective temperature stability. Measurements of a 130nm CMOS chip sh...
متن کاملExploiting the on-chip inductance in high-speed clock distribution networks
On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of desi...
متن کامل